Semi-Automated Design of a MOS Current Mode Logic Standard Cell Library from Generic Components

This paper describes the design and semi-automated generation of a MOS current-mode logic standard cell library. A set of generic components implementing a wide range of combinational and sequential functions is proposed. The layout of the generic components being parameterized for process design rules and transistor dimensions, the library can be mapped to different generations of CMOS processes. An implementation in 0.18um CMOS technology is presented

Towards a Unified Top-Down Design Flow for Fully-Differential Logic Blocks with Improved Speed and Noise Immunity

A new top-down design flow (RTL-to-GDSII) is proposed for achieving high-performance and noiseimmune designs consisting of differential logic blocks. The differential building blocks are based on the currentmode logic (CML), which offers true differentiality with low-swing signalling, switching-independent constant power dissipation and very high-speed operation. The goal of this flow is to allow effective cancellation of inductive and capacitive noise in high-speed on-chip interconnect lines using a simple generic interconnect architecture

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells

This paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers very high noise immunity due to the differential operation, as well as low production cost due to the via-programmable properties of the universal logic cell. Implementations of a number of circuits are presented and the area/speed performances are compared with classical CMOS implementation using a commercial standard cell library in 0.18 μm CMOS technology

Early Wire Characterization for Predictable Network-on-Chip Global Interconnects

This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for upcoming nanometer technologies, where increased variations in both device characteristics and interconnect parameters introduce tedious design closure problems. The proposed methodology has been successfully applied to the wire synthesis of a Network-on-Chip interconnect to: (i) achieve a given delay and noise goals, and (ii) attain a more power-efficient design with respect to existing techniques

A new interconnect-centric design methodology for high-speed standard cells with crosstalk immunity

One of the biggest challenges that are facing the Very Large Scale Integrated Circuits (VLSI) technologies today is the significant performance gap (3× to 9×) between full custom circuits and Application Specific Integrated Circuits (ASICs) designed in the same process generation. This situation is mainly exacurbated by the lack of suitable design tools and methodologies that can properly take into account the real implications and limitations of very deep submicron (VDSM) and nanometer scale technologies. The limitations are largely related to the signal integrity problems, caused by shrinking feature sizes with each new process. Crosstalk, for example, is one of the major issues because it results in unpredictable circuit behavior. This may cause significant timing variations, if not functional failures. Similarly, device and interconnect parasitics become harder to calculate, especially with irregular layout geometries. Accurate and early prediction of such problems, on the other hand, is virtually not possible with the existing tools. Meanwhile, the custom circuits become less affordable because of the skyrocketing design and manufacturing costs. At this point, the gate-array-like structures are becoming an increasingly popular alternative for rapid, low-cost realization of Integrated Circuits (ICs), filling the gap between Field-Programmable Gate-Arrays (FPGAs) and full-custom ASICs. In this work, the main goal is to provide an interconnect-centric design methodology, for which the underlying thinking is prevention over treatment of all these issues. Therefore, a "recipe" is described on how to early characterize these problems and address them even before they appear later during the implementation process. A simple generic RLCK interconnect model is developed and used to systematically characterize the interconnects of various geometries for delay, power and crosstalk noise. The superior performance of the differential interconnects in comparison to mainstream single-ended lines has lead to addressing the insufficient support of the Electronic Design Automation (EDA) tools for differential signaling. A complete RTL-to-GDSII differential design flow is developed that utilizes the advanced design tools through netlist conversion scripts. The advantages of differential signaling are merged with gate-level regularity in a mask-programmable cell fabric suitable for structured ASIC applications, where the basic building block is a via-programmable universal logic gate in MOS current-mode logic (MCML). The MCML design style offers good speed performance and addresses the noise immunity and crosstalk problems thanks to its differential operation. The unit cell can realize all functions up to 3-input and some of the 4-input and 5-input functions. The implementation of benchmark circuits with the proposed fabric have shown that the associated cost is acceptable when compared to the alternatives (standard-cell ASIC and FPGA). Finally, a novel design methodology is proposed which is based on correct-by-construction approach and is claimed to be a better candidate for future designs in nanometer technologies. The methodology is flexible in the sense that it makes it easier to model and to integrate emerging problems through its simulation based design exploration approach, which, in the scope of this thesis, has been focused on interconnect-related issues only. With case studies it is shown that the number of design flow iterations can be dramatically reduced or even removed by better guiding the physical implementation tools. The results dictate the EDA tools a number of advanced features to offer and/or the designers to more strongly utilize some of the existing tool capabilities, in order to manage the ever increasing design complexity

Via-Programmable Expanded Universal Logic Gate in MCML for Structured ASIC Applications: Part I - Circuit Design

This paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers high speed operation, very high noise immunity, as well as low production cost due to the via-programmable properties of the universal logic cell. Implementations of a number of circuits are presented and the area/speed performances are compared with a CMOS implementation using a commercial standard cell library in 0.18 um CMOS technology

Data_Sheet_2_Obstacles and expectations of rare disease patients and their families in Türkiye: ISTisNA project survey results.PDF

Rare disease patients constitute a significant part of the healthcare system of all countries. However, the information on the experiences during disease processes and daily life of rare disease patients is still limited. So far, there is a small number of studies conducted in Türkiye, and they mainly cover specific issues like education or anxiety. Here we present a comprehensive survey analysis conducted among the patients and their families within the scope of the Istanbul Solution Platform for Undiagnosed and Rare Diseases-ISTisNA project. A total of 498 individuals responded to the survey, and 58% of the participants answered all questions. The majority of the patients were in the age range of 1–10 years (44.7%), and 91% of all the patients had a precise diagnosis. The diagnosis rate in the first 6 months was 69%, and almost 10% of the patients remained undiagnosed. The mothers were the primary caregivers (72%). Nearly 30% of the caregivers had to quit their jobs and 25% of the patients (0–18 years) had to leave school. Accessing physicians with relevant specialization and reaching treatments/medications/supplements were the two main obstacles the participants mentioned, with a frequency of 81% and 73%, respectively. Around 50% of participants noted that they commonly faced difficulties at work/school and in their social lives. The highest expectation or priority was the establishment of rare disease-specific diagnosis and treatment centers, accurate and detailed information on diseases in the Turkish language, and easy access to physicians, treatments, and supportive therapies. To the best of our knowledge, this is the most comprehensive survey conducted on the rare disease community in Türkiye. These results show that regardless of the country, the individuals affected by rare diseases and their families have similar problems and expectations. On the other hand, regional and country-specific issues are still in the line to be solved. These studies can provide a deeper insight into rare diseases and guide the activities of Türkiye's national rare disease action plan.</p